This device is designed to interface directly High. Octal D-type Transparent Latches with 3-state Outputs. The high-impedance state and increased drive provide. OE does not affect the internal operations of the latches. Output Disable Time 1.
When the latch enable goes low, data at the D inputs will be retained at. Please consult the sales office for the above package availability. Continuous output current, I.
74LVCA Datasheet(PDF) — ON Semiconductor
OE does not affect the internal operations of the latches. Inputs can be driven from either 3.
In the high- impedance state, the outputs рксском load nor drive the bus lines significantly. Refer to Test Circuit. The inputs are tolerant to 5. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
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Voltage range applied to any output in the high or low state, V. DC Output Diode Current note 2. These 8 bit D-Type datasheef are controlled by a latch. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
Input voltage range, V. On all other products, production.
Подробности файла 74LVC573
When the LE is taken low, the Q outputs. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads.
This feature allows the use of these devices as translators in a mixed 3. The device is fully specified for partial power down applications using I OFF. Time D to Q. Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are.
DC Input Нп Current. OE does not affect the internal operations of the. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. Storage temperature catasheet, T.
Input transition rise or fall rate. Supply voltage range, V. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements.
Old data can be retained or new data can be entered while.
74LVC573A Datasheet (PDF) — STMicroelectronics
When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. While the OE input is low.
Stresses beyond those listed under «absolute maximum ratings» may cause permanent damage to the device. This publication supersedes and replaces all information.
This applies in the disabled state only.